This invention relates generally to signal acquisition and lock-on systems, and more particularly to a frequency and phase lock loop system for receiving RF signals.
A phase lock loop (PLL) is a feed back system typically comprising a phase detector or phase comparator, a PLL filter, and a voltage controlled oscillator (VCO). The VCO output signal is applied to one input terminal of a phase or frequency comparator, with an input reference signal being provided to the other input terminal of the phase or frequency comparator. The comparator generates an error signal, in response to phase or frequency differences between the VCO output signal and the reference signal. The error signal is applied to the PLL filter, the output signals of this filter being, in turn, applied to the control input of the VCO. By means of this feedback system the oscillator frequency approaches more closely and eventually locks onto the phase of the reference input signal by virtue of the correction signal fed back to the VCO.
The typical PLL has two modes of operation: signal acquisition, or frequency pull-in, and phase lock. In the acquisition mode the VCO's frequency is not equal to the input signal frequency and the loop generates a voltage which pulls the VCO frequency toward the input signal's frequency until it locks. The level of this stage of performance of the PLL is measured in terms of the maximum frequency acquisition range and the time required for signal pull-in. The second mode of PLL operation is termed phase lock which occurs when the VCO frequency and the input signal frequency are equal. Phase lock mode of operation is measured, or evaluated, in terms of PLL performance in the presence of noise. PLL performance in the presence of noise is determined by the closed loop noise bandwidth. Increased closed loop noise bandwidth results in increased PLL susceptibility to noise perturbation. To increase the PLL's frequency acquisition range, the cutoff frequency of the low pass loop filter is increased. However, this has the simultaneous undesirable effect of increasing the closed loop noise bandwidth thus decreasing PLL performance in the phase lock mode of operation. Thus, in prior art PLL systems a compromise between acquisition range and loop noise performance was required in optimizing PLL performance in a particular application.
Various approaches generally classified as either multiple loop systems or multiple mode systems have been proposed to improve performance of PLL systems. Quadricorrelators, swept or dithered VCO systems and frequency phase lock loops with frequency difference discriminators are some examples. These systems frequently do not lend themselves to integration, are often burdened with transitory discontinuities when changing modes, and do not fully achieve the goal of independent control over frequency acquisition and PLL performance characteristics.
A specific approach to improving FPLL performance is disclosed in U.S. Pat. No. 4,072,909 to Citta which discloses an automative phase and frequency control system. Briefly, this system includes two multipliers coupled to the input, or received, signal and to quadrature phase shifting means for phase shifting the output of the VCO to the multiplier combination thus producing a pair of quadrature phase related beat signals together with sum signals. The sum signals are filtered out while the beat signal output of one multiplier is coupled to one input of a third multiplier with the quadrature beat signal of the other multiplier converted by limiter circuitry and a low pass filter to a constant amplitude signal which is provided to the other input terminal of the third multiplier. With the low pass filter possessing a predetermined phase versus frequency characteristic, the filter (and also the limiter) output signal undergoes a phase delay which is a function of the signal frequency. Multiplication of the squared output signal of the limiter and the sinusoidal-like beat signal output of the first multiplier produces an error signal of constant amplitude having a DC component which varies with beat signal frequency. This DC component is then filtered and fed back to the VCO permitting input signal acquisition and normal phase lock operation when the frequencies of the VCO and the input signal are equal resulting in a DC output voltage signal from the limiter. This system represents a substantial improvement in automatic phase and frequency control systems in that substantial independence between signal acquisition and phase lock parameters is achieved.
While a large signal acquisition range and stable phase lock loop operation is attainable in the automatic phase and frequency control system described and claimed in the referenced patent, the degree to which independent control over the frequency acquisition and loop noise performance can be exercised is limited. The feedback signal in this system includes AC components which include harmonics of the beat frequency. As the difference frequency between the input and VCO signals become smaller, the AC loop gain increases with these harmonics increasing in strength. Not only do these beat frequency harmonics increase in amplitude thus producing unwanted sidebands around the VCO center frequency, but the fundamental beat frequency is lost from the VCO control signal. The absence of the fundamental beat frequency is due to the "chopping" effect of the frequency loop multiplier on the beat note signal and limits PLL performance. More specifically, the restriction on the independent control of frequency acquisition and PLL parameters results in the requirement that the residual frequency error of the frequency acquisition part of the system must be less than the lock-in range of the PLL in order for phase lock to occur within one beat cycle.
These and other problems experienced in the above-discussed Citta patent are eliminated in the present invention which is not only capable of being implemented as an IC, but also is capable of improved signal pull-in range and possesses an infinite figure of merit. This is accomplished by the total separation of acquisition and phase lock functions in the frequency and phase lock loop with separated AFC and phase locking of the present invention.